SHARC - Simulation and Verification of Hierarchical Embedded Microelectronic Systems

Hierarchical Modeling and Verification of Embedded Systems

In order to represent efficiently large systems, a mechanism for hierarchical composition is needed so that the model may be constructed in a structured manner and composed of simpler units easily comprehensible by the designer at each description level. In this paper we formally define the notion of hierarchy for a Petri net based representation used for modeling embedded systems. We show how ...

Hierarchical Integrated Simulation Techniques for the Design of Embedded Systems

Runtime verification and monitoring of embedded systems

Ensuring the correctness of software applications is a difficult task. The area of runtime verification, which combines the approaches of formal verification and testing, offers a practical but limited solution that can help in finding many errors in software. Runtime verification relies upon tools for monitoring software execution. There are particular difficulties with regard to monitoring em...

Hierarchical modeling and analysis of embedded systems

This paper describes the modeling language CHARON for modular design of interacting hybrid systems. The language allows specification of architectural as well as behavioral hierarchy and discrete as well as continuous activities. The modular structure of the language is not merely syntactic, but is exploited by analysis tools and is supported by a formal semantics with an accompanying compositi...

Verification Tools for Embedded Systems

We propose a five-year research initiative at Carnegie Mellon University to create a new generation of formal verification tools that can be integrated into design environments for the complex, high-assurance embedded systems that will be required by future military systems. These systems are increasingly distributed, complex dynamic systems that must operate with a high degree of autonomy and ...